There are various basic CMOS pixel structures. One common type, with 3 transistors per pixel, is described in U.S. Pat. No. 4,407,010 (referred to as the CMOS 3T pixel), and is illustrated in FIG. 1 of the accompanying drawings. This is an efficient structure, wherein transistor M1 amplifies an output from the photodiode while positioned within the pixel. Transistor M2 resets the voltage on the pixel, and transistor M3 is a multiplex transistor. Transistor M3 enables many pixels in a column to be wired together, and only one pixel is enabled at a time. The device Iload is typically a sense amplifier that provides a load for the source follower transistor M1, and also measures the output voltage.
The typical voltage on a photodiode is shown in FIG. 2. At point 1, the pixel is reset by turning on transistor M2 which sets the voltage on the reverse-biased diode to a preset voltage (VRT). After this point, light falling onto the pixel will create photo-generated electrons which will be attracted to the photodiode. This will cause the diode to be discharged. The amount of discharge is proportional to both the amount of light and also the amount of time. After a period of time (integration period Tint) the voltage on the pixel is measured. If the time Tint is kept constant, the swing will be proportional solely to the amount of light falling on the pixel.
Typically, as shown in FIG. 3, the pixels are arranged into a 2-dimensional grid of rows and columns. There is one Iload/sense amplifier per column. The amplifier measures the output voltage of the pixel. Several pixels and usually all the pixels in a column share a single sense amplifier. Because of this structure, all the elements in a row are read out simultaneously into the sense amplifiers and the rows are addressed sequentially.
As the rows are read out sequentially, they must also be reset sequentially. This keeps the integration time Tint constant for the whole sensor, and the brightness of the image constant over the image plane. This operation is called “rolling blade shutter” and is analogous to how a physical shutter in a 35 mm SLR camera works. In the CMOS 3T sensor, the integration time is variable. This is achieved by varying the time between the reset and readout pulse. This is also similar to how 35 mm SLR cameras work. The shutter blades move over the film at a constant rate, but a gap between the blades is adjusted to adjust the effective shutter speed.
Another common type of CMOS pixel has 4 transistors. There are various types of implementation, one of which is shown in FIG. 4. The advantage of this design is that it has two storage capacitances per pixel. Cpd is formed by the parasitic capacitance of the photodiode. The storage node Csn is formed partly by the stray capacitance of M1, M2 but also by creating a storage device inside the pixel. One advantage of a 4T pixel is sensitivity: V=Q/C. By reducing the value of Csn, the output voltage for a given photocharge is increased.
The 4T pixel has another advantage, which is its ability to form an electronic shutter. Although arrays of either 3T or 4T pixels can be reset simultaneously, the sequential readout mechanism of the 3T pixel prevents simultaneous readout. The 4T pixel does not suffer from this problem since it has a storage element incorporated inside each pixel (Csn in FIG. 4). This permits the entire array to be sensed simultaneously, i.e., a photo-generated charge is transferred from each pixel's Cpd to the pixel's Csn simultaneously.
The readout mechanism then proceeds in a row sequential fashion, similar to the mechanism used in the 3T pixels. As all the pixels in the array are reset and measured simultaneously, the array captures a snapshot of the light pattern falling on the sensor, unlike the rolling blade shutter of the 3T pixels. This technique is of great value for hand-held operation of the camera as the effect of camera shake is reduced as the total time for which the array is collecting light is minimized, as opposed to the time for which an individual pixel is collecting light.
There are significant disadvantages with a 4T pixel. The extra circuitry (M4, Csn) occupies an area on the pixel and this reduces the amount of light reaching the photodiode. Transferring all the charge from Cpd to Csn is difficult to achieve. Special CMOS manufacturing techniques are often employed to change the structure of the photodiode Cpd or the transfer transistor M4. These manufacturing techniques are very costly since as they are non-standard and are also difficult to reliably achieve.
There are also some linear arrays (see FIG. 5) with two rows of pixels which have separate electronics on both top and bottom. However, these structures are limited to a maximum of two rows. Other prior art in this area includes U.S. Pat. Nos. 4,835,617; 5,576,762; 5,134,489; 5,122,881; 5,471,515, and European Patent WO 98/08079.